A CMOS image sensor with improved readout speed using column SAR ADC with digital error correction

Abstract

This paper proposes a CMOS image sensor (CIS) whose readout speed is improved by 33%, through applying a digital error correction (DEC) method to its column-level successive approximation register (SAR) analog to digital converters (ADC), compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC's incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC's linearity of 10 bit within a 5 bit accuracy's settling time. Simulation results show the DEC method improves the ADC's static and dynamic linearity, eliminating its missing codes and increasing its signal to noise plus distortion ratio (SNDR) from 64.5 dB to 67.5 dB, when operating at the same sampling speed. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC, while increasing the sampling rate by 33 %. The simulated linearity of the prototype CIS is within ±0.07 %, when sampled at a column readout rate of 10 MHz.