This letter introduces a Gm-cell-based CMOS image sensor (CIS) achieving deep subelectron noise performance. The CIS presents a new compensation block and low-noise current source to improve the performance of the Gm pixel. Furthermore, an optional first-order IIR filter is implemented to improve the output swing. The conversion gain, full well capacity, and dynamic range of the CIS can be easily adjusted by the charging time and the filter mode for different applications. The prototype chip is fabricated in a standard 180 nm CIS process and has a deep subelectron read noise of 0.31e-rms at minimum (of the noise distribution) and 0.42e-rms at peak (of the noise distribution). A smooth and clear photon-counting histogram is observed.

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This paper focuses on a new non-ideal phenomenon induced by the power supply crosstalk (PSC) of the row drive circuit in 8 T global shutter (GS) CMOS image sensors (CISs). A method to eliminate the non-ideal phenomenon is presented. Based on the circuit simulation, the relationship between the parasitic resistance and PSC is analyzed. The PSC would cause a charge leakage on the sampling hold (S/H) capacitors in the 8 T pixel, which in turn attenuates the output signal of the image sensor. Through the mathematical model of the in-pixel S/H circuit, the effect of PSC and exposure on signal attenuation is analyzed. To eliminate signal attenuation, this paper utilizes a separate power layout method that isolates the row drivers in different columns by using multiple power supplies. In contrast to the method of sharing the power supply, the proposed method can reduce the maximum power supply crosstalk noise from 1.17 V to 2.58 μV in the 2000 × 2 row drive array. Based on the 0.13 μm CMOS process, the measurement results of the 1st chip design using the typical shared power structure and the 2nd chip design using the separate power supply structure are compared. The measurement results show that the output signal of the 1st chip design is limited to about 303 ADU due to the power supply crosstalk. The saturated output signal of the 2nd chip design is 2200 ADU, which is in accordance with the theoretical signal output value (2200 ADU) when the pixel is saturated. The proposed method can effectively eliminate signal attenuation induced by the PSC, thereby improving the image quality of 8 T GS CIS.

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To improve charge transfer efficiency (CTE) and eliminate image lag, the impact of spill back effect on image lag is studied in CMOS image sensors (CISs), particularly in high illumination condition. By establishing a mathematical model based on the thermionic emission and drift-diffusion theory, the physical mechanism of spill back effect is described. This model shows that a lower transfer gate (TG) operating voltage and a higher reset voltage of Floating Diffusion (FD) node would mitigate spill back effect. In a 0.18 μ m CMOS process, by setting that the gate voltage of transfer transistor and the reset voltage of FD is 2.8 V and 3.8 V respectively, CTE of the proposed pixel is increased to 100%. The theoretical analysis and TCAD simulation results can explain spill back effect and offer a reference for designing a high CTE pixel in high illumination CISs.

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To improve the full-well capacity and linear dynamic range of CMOS image sensor, a special finger-shaped pinned photodiode (PPD) is designed. In terms of process, the first N-type ion implantation of the PPD N buried layer is extended under the transfer gate, thereby increasing the PPD capacitance. Based on TCAD simulation, the width and spacing of PPD were precisely adjusted. A high full-well capacity pixel design with a pixel size of 6 × 6 μm2 is realized based on the 0.18 μm CMOS process. The simulation results indicate that the pixel with the above structure and process has a depletion depth of 2.8 μm and a charge transfer efficiency of 100%. The measurement results of the test chip show that the full-well capacity can reach 68650e-. Compared with the conventional structure, the proposed PPD structure can effectively improve the full well capacity of the pixel.@en

This paper presents a highly linear CMOS image sensor (CIS) designed in a commercial 0.18-μ m CIS technology. A new type of pixel is proposed based on the linearity analysis of a conventional 4T active pixel. The new type of pixel can mitigate the nonlinearity caused by the in-pixel source follower (SF) transistor. In addition, the optimization of the pixel design, a digitally assisted calibration method is proposed to further reduce the nonlinearity of the image sensor, especially, the nonlinearity caused by the integration capacitor (C_FD) on the floating diffusion (FD) node. A hybrid behavioral model is proposed to validate the calibration method. Experimental results show that the new type of pixel has a better linearity performance comparing with that of the typical 4T pixel. TCAD simulation results are used to help explain the spillback effect in the transfer transistor's channel. With the digital calibration, the linearity performances of the pixels in different settings have been improved.

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Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.@en