Analysis and Modeling of Spill Back Effect in High Illumination CMOS Image Sensors

Journal article (2020)

Authors

Jiangtao Xu Tianjin University
Ruishuo Wang Tianjin University
L. Han Electronic Instrumentation - EEMCS
Zhiyuan Gao Guangdong University of Technology
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Charge transfer Spill back CMOS image sensors (CISs) Image lag
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Published Date

2020

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

To improve charge transfer efficiency (CTE) and eliminate image lag, the impact of spill back effect on image lag is studied in CMOS image sensors (CISs), particularly in high illumination condition. By establishing a mathematical model based on the thermionic emission and drift-diffusion theory, the physical mechanism of spill back effect is described. This model shows that a lower transfer gate (TG) operating voltage and a higher reset voltage of Floating Diffusion (FD) node would mitigate spill back effect. In a 0.18 μ m CMOS process, by setting that the gate voltage of transfer transistor and the reset voltage of FD is 2.8 V and 3.8 V respectively, CTE of the proposed pixel is increased to 100%. The theoretical analysis and TCAD simulation results can explain spill back effect and offer a reference for designing a high CTE pixel in high illumination CISs.

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