Analysis of signal attenuation in global shutter CMOS image sensor

Abstract

This paper focuses on a new non-ideal phenomenon induced by the power supply crosstalk (PSC) of the row drive circuit in 8 T global shutter (GS) CMOS image sensors (CISs). A method to eliminate the non-ideal phenomenon is presented. Based on the circuit simulation, the relationship between the parasitic resistance and PSC is analyzed. The PSC would cause a charge leakage on the sampling hold (S/H) capacitors in the 8 T pixel, which in turn attenuates the output signal of the image sensor. Through the mathematical model of the in-pixel S/H circuit, the effect of PSC and exposure on signal attenuation is analyzed. To eliminate signal attenuation, this paper utilizes a separate power layout method that isolates the row drivers in different columns by using multiple power supplies. In contrast to the method of sharing the power supply, the proposed method can reduce the maximum power supply crosstalk noise from 1.17 V to 2.58 μV in the 2000 × 2 row drive array. Based on the 0.13 μm CMOS process, the measurement results of the 1st chip design using the typical shared power structure and the 2nd chip design using the separate power supply structure are compared. The measurement results show that the output signal of the 1st chip design is limited to about 303 ADU due to the power supply crosstalk. The saturated output signal of the 2nd chip design is 2200 ADU, which is in accordance with the theoretical signal output value (2200 ADU) when the pixel is saturated. The proposed method can effectively eliminate signal attenuation induced by the PSC, thereby improving the image quality of 8 T GS CIS.