A linearity improvement method for CIS column-parallel SAR ADC using two-step conversion

Conference paper (2023)

Authors

J. Lee Electronic Instrumentation - EEMCS
A.J.P.A.M. Theuwissen Electronic Instrumentation - EEMCS , Harvest Imaging
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Copyright: © 2023 J. Lee, A.J.P.A.M. Theuwissen
DOI
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https://doi.org/10.1109/ESSCIRC59616.2023.10268814
CMOS Image Sensor SAR ADC Linearity Column-parallel structure
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a new 2-step SAR ADC architecture for image sensors in machine vision applications. This structure effectively improves the structural problems of the image sensor caused by the area occupied by the ADC, such as linearity and temporal noise performance. In this work, we designed a two-step SAR ADC using a 6-bit SAR ADC and a PGA generating residue and offset. Since the number of unit capacitor's is reduced, the common centroid method is applied in the capacitor layout to improve the linearity. As a result, the capacitor mismatch characteristic is improved, and the differential nonlinearity (DNL) obtained is +0.36/-0.28LSB. In addition, the temporal noise is about 530 μ Vrns due to the small bandwidth of the column-parallel structure in an image sensor. The implemented ADC achieves 250 kS/ s as a maximum speed. The maximum frame rate of the sensor is 2500fps. The power consumption of the sensor, except for the LVDS interface, is 37.5 ∼mW. This sensor is designed in TowerJazz CIS 180 ∼nm process with one poly and four metal layers. The supply voltage of the analog and digital domains are 3.3 ∼V and 1.8 ∼V, respectively.