JL
J. Lee
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1
High Speed readout architecture for CMOS image sensor
A dual approach using adaptive reconfigurable Systems and low-power sar ADCS
This thesis presents a comprehensive study on enhancing the frame rate of CMOS image sensors through both circuit-level and system-level innovations. Motivated by the growing demands inmachine vision and artificial intelligence applications such as ADAS and industrial automation, this work addresses the limitations of conventional high-speed image sensor designs, which typically require increased ADC sampling rates or a higher number of ADCs—often leading to trade-offs in area, power consumption, and image quality.
The first contribution of this research lies in the analog front-end design, particularly in optimizing the ADC architecture. A column-parallel SAR ADC is developed, with both conventional and advanced two-step structures implemented to reduce noise, improve linearity, and minimize layout area. These ADCs are designed to operate efficiently at 250kS/s while maintaining low temporal noise. Techniques such as analog correlated double sampling (CDS), comparator offset calibration, and FPN suppression using optical black (OB) pixels are applied to ensure image quality despite the high-speed operation. The overall noise model is theoretically analyzed and validated, showing that with proper bandwidth and CDS timing, temporal noise remains within acceptable limits without requiring high-frequency operation.
Beyond the circuit-level improvements, a major innovation is the implementation of an adaptive reconfigurable system that switches between full-frame and region-ofinterest (ROI) modes. Recognizing that in many practical scenarios—such as tracking a moving object in a fixed background—only a small part of the image needs to be updated, the proposed system dynamically identifies and captures a small ROI (e.g., 10×10 pixels) around the object. By capturing multiple ROI images within a single full-frame cycle, the effective frame rate is dramatically improved without increasing ADC speed or interface bandwidth. The intelligent switch network, pixel array design, and address decoder architecture are all tailored to support seamlessmode switching, enabling up to 750,000fps in effective frame ratewhile operating under fixed ADC sampling constraints.
The image data path, from pixel readout to ADC conversion and digital transmission, is carefully coordinated. In zoom-in mode, 300 ADCs sample and convert ROI data across three separate sets per horizontal line, managed by FPGA-controlled timing. Image data is reassembled and analyzed in real-time within the FPGA to update the ROI position based on intensity variation. The image analyzer performs high-speed comparison using a sliding 10×10 mask and updates ROI coordinates frame-by-frame. This feedback loop ensures accurate object tracking while minimizing redundant data processing.
Measurement results confirm that the proposed design successfully achieves highspeed performance and high image quality with improved energy efficiency. The background offset calibration achieves VFPN levels as low as 0.37LSB, and the system avoids the power and timing penalties typically associated with high-speed ADC operation and high-throughput interfaces. The architecture demonstrates a scalable, application-specific approach to image sensor design, suitable for future intelligent sensing systems.
In summary, this thesis delivers a novel image sensor readout architecture that enhances frame rate without compromising image quality or power efficiency. It introduces a practical framework for high-speed operation through a dual approach: a compact, high-performance SAR ADC and a flexible reconfigurable system architecture. Together, these solutions forma robust platformfor next-generation machine vision applications that demand both speed and intelligence. ...
The first contribution of this research lies in the analog front-end design, particularly in optimizing the ADC architecture. A column-parallel SAR ADC is developed, with both conventional and advanced two-step structures implemented to reduce noise, improve linearity, and minimize layout area. These ADCs are designed to operate efficiently at 250kS/s while maintaining low temporal noise. Techniques such as analog correlated double sampling (CDS), comparator offset calibration, and FPN suppression using optical black (OB) pixels are applied to ensure image quality despite the high-speed operation. The overall noise model is theoretically analyzed and validated, showing that with proper bandwidth and CDS timing, temporal noise remains within acceptable limits without requiring high-frequency operation.
Beyond the circuit-level improvements, a major innovation is the implementation of an adaptive reconfigurable system that switches between full-frame and region-ofinterest (ROI) modes. Recognizing that in many practical scenarios—such as tracking a moving object in a fixed background—only a small part of the image needs to be updated, the proposed system dynamically identifies and captures a small ROI (e.g., 10×10 pixels) around the object. By capturing multiple ROI images within a single full-frame cycle, the effective frame rate is dramatically improved without increasing ADC speed or interface bandwidth. The intelligent switch network, pixel array design, and address decoder architecture are all tailored to support seamlessmode switching, enabling up to 750,000fps in effective frame ratewhile operating under fixed ADC sampling constraints.
The image data path, from pixel readout to ADC conversion and digital transmission, is carefully coordinated. In zoom-in mode, 300 ADCs sample and convert ROI data across three separate sets per horizontal line, managed by FPGA-controlled timing. Image data is reassembled and analyzed in real-time within the FPGA to update the ROI position based on intensity variation. The image analyzer performs high-speed comparison using a sliding 10×10 mask and updates ROI coordinates frame-by-frame. This feedback loop ensures accurate object tracking while minimizing redundant data processing.
Measurement results confirm that the proposed design successfully achieves highspeed performance and high image quality with improved energy efficiency. The background offset calibration achieves VFPN levels as low as 0.37LSB, and the system avoids the power and timing penalties typically associated with high-speed ADC operation and high-throughput interfaces. The architecture demonstrates a scalable, application-specific approach to image sensor design, suitable for future intelligent sensing systems.
In summary, this thesis delivers a novel image sensor readout architecture that enhances frame rate without compromising image quality or power efficiency. It introduces a practical framework for high-speed operation through a dual approach: a compact, high-performance SAR ADC and a flexible reconfigurable system architecture. Together, these solutions forma robust platformfor next-generation machine vision applications that demand both speed and intelligence. ...
This thesis presents a comprehensive study on enhancing the frame rate of CMOS image sensors through both circuit-level and system-level innovations. Motivated by the growing demands inmachine vision and artificial intelligence applications such as ADAS and industrial automation, this work addresses the limitations of conventional high-speed image sensor designs, which typically require increased ADC sampling rates or a higher number of ADCs—often leading to trade-offs in area, power consumption, and image quality.
The first contribution of this research lies in the analog front-end design, particularly in optimizing the ADC architecture. A column-parallel SAR ADC is developed, with both conventional and advanced two-step structures implemented to reduce noise, improve linearity, and minimize layout area. These ADCs are designed to operate efficiently at 250kS/s while maintaining low temporal noise. Techniques such as analog correlated double sampling (CDS), comparator offset calibration, and FPN suppression using optical black (OB) pixels are applied to ensure image quality despite the high-speed operation. The overall noise model is theoretically analyzed and validated, showing that with proper bandwidth and CDS timing, temporal noise remains within acceptable limits without requiring high-frequency operation.
Beyond the circuit-level improvements, a major innovation is the implementation of an adaptive reconfigurable system that switches between full-frame and region-ofinterest (ROI) modes. Recognizing that in many practical scenarios—such as tracking a moving object in a fixed background—only a small part of the image needs to be updated, the proposed system dynamically identifies and captures a small ROI (e.g., 10×10 pixels) around the object. By capturing multiple ROI images within a single full-frame cycle, the effective frame rate is dramatically improved without increasing ADC speed or interface bandwidth. The intelligent switch network, pixel array design, and address decoder architecture are all tailored to support seamlessmode switching, enabling up to 750,000fps in effective frame ratewhile operating under fixed ADC sampling constraints.
The image data path, from pixel readout to ADC conversion and digital transmission, is carefully coordinated. In zoom-in mode, 300 ADCs sample and convert ROI data across three separate sets per horizontal line, managed by FPGA-controlled timing. Image data is reassembled and analyzed in real-time within the FPGA to update the ROI position based on intensity variation. The image analyzer performs high-speed comparison using a sliding 10×10 mask and updates ROI coordinates frame-by-frame. This feedback loop ensures accurate object tracking while minimizing redundant data processing.
Measurement results confirm that the proposed design successfully achieves highspeed performance and high image quality with improved energy efficiency. The background offset calibration achieves VFPN levels as low as 0.37LSB, and the system avoids the power and timing penalties typically associated with high-speed ADC operation and high-throughput interfaces. The architecture demonstrates a scalable, application-specific approach to image sensor design, suitable for future intelligent sensing systems.
In summary, this thesis delivers a novel image sensor readout architecture that enhances frame rate without compromising image quality or power efficiency. It introduces a practical framework for high-speed operation through a dual approach: a compact, high-performance SAR ADC and a flexible reconfigurable system architecture. Together, these solutions forma robust platformfor next-generation machine vision applications that demand both speed and intelligence.
The first contribution of this research lies in the analog front-end design, particularly in optimizing the ADC architecture. A column-parallel SAR ADC is developed, with both conventional and advanced two-step structures implemented to reduce noise, improve linearity, and minimize layout area. These ADCs are designed to operate efficiently at 250kS/s while maintaining low temporal noise. Techniques such as analog correlated double sampling (CDS), comparator offset calibration, and FPN suppression using optical black (OB) pixels are applied to ensure image quality despite the high-speed operation. The overall noise model is theoretically analyzed and validated, showing that with proper bandwidth and CDS timing, temporal noise remains within acceptable limits without requiring high-frequency operation.
Beyond the circuit-level improvements, a major innovation is the implementation of an adaptive reconfigurable system that switches between full-frame and region-ofinterest (ROI) modes. Recognizing that in many practical scenarios—such as tracking a moving object in a fixed background—only a small part of the image needs to be updated, the proposed system dynamically identifies and captures a small ROI (e.g., 10×10 pixels) around the object. By capturing multiple ROI images within a single full-frame cycle, the effective frame rate is dramatically improved without increasing ADC speed or interface bandwidth. The intelligent switch network, pixel array design, and address decoder architecture are all tailored to support seamlessmode switching, enabling up to 750,000fps in effective frame ratewhile operating under fixed ADC sampling constraints.
The image data path, from pixel readout to ADC conversion and digital transmission, is carefully coordinated. In zoom-in mode, 300 ADCs sample and convert ROI data across three separate sets per horizontal line, managed by FPGA-controlled timing. Image data is reassembled and analyzed in real-time within the FPGA to update the ROI position based on intensity variation. The image analyzer performs high-speed comparison using a sliding 10×10 mask and updates ROI coordinates frame-by-frame. This feedback loop ensures accurate object tracking while minimizing redundant data processing.
Measurement results confirm that the proposed design successfully achieves highspeed performance and high image quality with improved energy efficiency. The background offset calibration achieves VFPN levels as low as 0.37LSB, and the system avoids the power and timing penalties typically associated with high-speed ADC operation and high-throughput interfaces. The architecture demonstrates a scalable, application-specific approach to image sensor design, suitable for future intelligent sensing systems.
In summary, this thesis delivers a novel image sensor readout architecture that enhances frame rate without compromising image quality or power efficiency. It introduces a practical framework for high-speed operation through a dual approach: a compact, high-performance SAR ADC and a flexible reconfigurable system architecture. Together, these solutions forma robust platformfor next-generation machine vision applications that demand both speed and intelligence.
This paper presents a new 2-step SAR ADC architecture for image sensors in machine vision applications. This structure effectively improves the structural problems of the image sensor caused by the area occupied by the ADC, such as linearity and temporal noise performance. In this work, we designed a two-step SAR ADC using a 6-bit SAR ADC and a PGA generating residue and offset. Since the number of unit capacitor's is reduced, the common centroid method is applied in the capacitor layout to improve the linearity. As a result, the capacitor mismatch characteristic is improved, and the differential nonlinearity (DNL) obtained is +0.36/-0.28LSB. In addition, the temporal noise is about 530 μ Vrns due to the small bandwidth of the column-parallel structure in an image sensor. The implemented ADC achieves 250 kS/ s as a maximum speed. The maximum frame rate of the sensor is 2500fps. The power consumption of the sensor, except for the LVDS interface, is 37.5 ∼mW. This sensor is designed in TowerJazz CIS 180 ∼nm process with one poly and four metal layers. The supply voltage of the analog and digital domains are 3.3 ∼V and 1.8 ∼V, respectively.
...
This paper presents a new 2-step SAR ADC architecture for image sensors in machine vision applications. This structure effectively improves the structural problems of the image sensor caused by the area occupied by the ADC, such as linearity and temporal noise performance. In this work, we designed a two-step SAR ADC using a 6-bit SAR ADC and a PGA generating residue and offset. Since the number of unit capacitor's is reduced, the common centroid method is applied in the capacitor layout to improve the linearity. As a result, the capacitor mismatch characteristic is improved, and the differential nonlinearity (DNL) obtained is +0.36/-0.28LSB. In addition, the temporal noise is about 530 μ Vrns due to the small bandwidth of the column-parallel structure in an image sensor. The implemented ADC achieves 250 kS/ s as a maximum speed. The maximum frame rate of the sensor is 2500fps. The power consumption of the sensor, except for the LVDS interface, is 37.5 ∼mW. This sensor is designed in TowerJazz CIS 180 ∼nm process with one poly and four metal layers. The supply voltage of the analog and digital domains are 3.3 ∼V and 1.8 ∼V, respectively.
A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.
...
A column-parallel 10-bit SAR ADC for high-speed image sensors has been implemented. A fast offset calibration technique using memory is proposed to compensate for the offset mismatch, accompanied by an ADC designed for a narrow space the size of a single column pitch. The memory accumulates the variation of the offset to track the offset within two cycles. After applying the offset calibration technique, the offset variation of the ADC measured in each column is improved from 4.27LSB to 0.39LSB. The fixed-pattern noise (FPN) is also improved from 4.14LSB to 0.34LSB. This calibration method covers an offset range of ±32LSB. The implemented ADC achieves a maximum speed of 500kS/s. The maximum frame rate of the sensor is 3000fps. The power consumption of the sensor, excluding the LVDS interface, is 71mW. This sensor is designed in a TowerJazz CIS 180nm process with one poly four metal. The supply voltage of the analog and digital domains is 3.3V and 1.8V, respectively.