High-speed and low-power Graphene ADC with scalable resolution

Abstract

This paper introduces a novel scalable resolution graphene Analog-to-Digital Converter (ADC) architecture that relies on an adaptive binary search, i.e., the output bits are serially computed starting from MSB, while at each iteration the previous result is utilized to drive the binary search and obtain the next bit value. Its implementation relies on custom crafted Graphene Nanoribbon (GNR) devices able to provide augmented analog functionality (more complex than GNR transistors), in order to attain low-power and high-speed conversion capabilities. The GNR devices are arranged in a complementary design style (akin to Boolean logic with pull-up network and pull-down network), to increase robustness and yield a power consumption friendly voltage-mode operation. As a result, the proposed ADC architecture requires a constant area of only 6 GNR devices, and scales linearly speed-wise with n, the ADC resolution. To demonstrate our approach, we present a 4-bit ADC circuit implementation able to convert input voltages V_in ∈ [0,100mV] while operating with a supply voltage V_DD = 200mV. We demonstrate ADC's correct functionality by means of SPICE simulations and compare it with state-of-the-art counterparts. Simulation results indicate that the ADC achieves a sampling rate of 25Gs/s, is low power (40nW), while occupying an active area of only 0.22nm², and features a Schreier FoM of 198.3dB and a Walden FoM of 0.186fJ/step. When compared with recent prior art the 4-bit GNR ADC requires 6 to 8 orders lower area and 6 orders of magnitude lower power at comparable speed, which result in 2 to 3 orders of magnitude lower energy consumption per conversion. Finally, we discuss resolution scalability impact on area, power consumption, and sample rate asymptotic complexities of our proposal vs state-of-the-art counterparts. Our analysis indicates that due to its O(1) area and power consumption, and O( n ) sampling rate the proposed ADC opens new design avenues within the current ADC architectures landscape, where high resolution is usually traded either for very low sampling rate or for high power.