A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

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A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Conference Paper (2017)

Author(s)

Pierluigi Cenci (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Muhammed Bolatkale (NXP Semiconductors, TU Delft - Electrical Engineering, Mathematics and Computer Science)

Robert Rutten (NXP Semiconductors)

Gerard Lassche (Catena)

Kofi Makinwa (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Lucien Breems (NXP Semiconductors, Eindhoven University of Technology)

Research Group

Electronic Instrumentation

Asynchronous logic 28 nm CMOS SAR converter Single-channel Rail-to-rail input signal Bottom plate sampling Gm-boosted StrongARM comparator

DOI related publication

https://doi.org/10.1109/ESSCIRC.2017.8094553 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:8bbc1c41-b4c6-499a-b697-90b783206c4c

More Info

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Publication Year

2017

Language

English

Research Group

Electronic Instrumentation

Pages (from-to)

171-174

ISBN (electronic)

978-1-5090-5025-3

Event

ESSDERC-ESSCIRC 2017 (2017-09-11 - 2017-09-14), Leuven, Belgium

Downloads counter

268

Abstract

This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.