A 28 nm 2 GS/s 5-b single-channel SAR ADC with gm-boosted StrongARM comparator

Conference paper (2017)

Authors

P. Cenci Electronic Instrumentation - EEMCS
M. Bolatkale Electronic Instrumentation - EEMCS , NXP Semiconductors
Robert Rutten NXP Semiconductors
K.A.A. Makinwa Microelectronics
L Breems Eindhoven University of Technology, NXP Semiconductors
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
Asynchronous logic 28 nm CMOS SAR converter Single-channel Rail-to-rail input signal Bottom plate sampling Gm-boosted StrongARM comparator
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper presents a 2 GS/s 5-b single-channel SAR ADC in 28 nm CMOS. The ADC uses a gm-boosted StrongARM comparator to achieve the highest reported sampling frequency for a non-time-interleaved SAR ADC. Its high sampling frequency, large input signal capability and one clock cycle latency make the ADC suitable for time-interleaved, multi-stage and feedback ADC architectures. The ADC occupies 900 μm2 and consumes 1.25 mW from a 0.9 V supply. Without calibration, and when operated at 1.5 GS/s it achieves 30.3 dB SNDR (FOMw=31.2 fJ/conv.-step). This drops slightly, to 27.4dB, at the maximum sampling rate of 2 GS/s.

Files

08094553.pdf
(.pdf | 1.57 Mb)