Instruction cache aging mitigation through Instruction Set Encoding

Abstract

The reliability of embedded processors fabricated using nanoscale technology nodes is threatened by accelerated transistor aging particularly, Bias Temperature Instability (BTI). In embedded memories such as instruction caches, BTI degrades the Static Noise Margin (SNM) of the memory cell, which in turn affects the stability of the stored value. Various bit flipping based solutions have been proposed to address BTI-induced aging of memory components. Nevertheless, the state-of-the-art techniques have considerable area and power overheads. In this paper, we propose an aging-aware instruction encoding technique to mitigate BTI-induced aging of instruction caches. Opcode, register and function code fields of an instruction are re-encoded so that the BTI-induced aging of the instruction cache is minimized. Simulation results show that the proposed technique achieves up to 40% SNM degradation improvement (equivalent to 47% MTTF improvement) with a negligible power overhead (0.1%).