Pre-Synthesis Evaluation of Digital Bus Micro-Architectures

Abstract

Buses are central building blocks in the architecture of digital systems. There are numerous standards for bus architectures and evaluation metrics in terms of data transfer rate, quality of service, and latency; however, it is not common to find metrics related to the physical features of bus implementations, such as power consumption and area in terms of their microarchitecture. This paper evaluate bus micro-architectures at pre-synthesis level, allowing for the comparison of alternative circuits implementing the same standard and thus providing estimations on the power consumption and area requirements. A metric is proposed to evaluate the bus implementation and its utilization is shown with generic serial and parallel buses, based on simulations with a 0.18μm CMOS standard cell library.