DRAM fault analysis and test generation

Abstract

Dynamic random access memories (DRAMs) are the most widely used type of memory in the market today, due to their important application as the main memory of the personal computer (PC). These memories are tested by their manufacturers in an ad hoc way, that results in an expensive test process the price of which is ultimately paid by the end consumer. In this PhD dissertation, we propose a new alternative approach to the development of industrial memory testing that is more systematic and less expensive than the currently used test approaches. The new approach is based on the introduction of a number of fault analysis algorithms that enable using electrical Spice simulations to develop effective memory tests in a short amount of time. The new approach makes it possible to enhance memory tests in many different manufacturing stages, starting from the initial test application stage where silicon is manufactured, through the memory ramp-up stage where products are shipped to the customer, and ending with the test adaptation stage, based on memory failures in the field. The new test development approach has been implemented and evaluated at Infineon Technologies, a leading DRAM manufacturer based in Germany, to develop tests for their DRAM products.