Leveraging the Openness and Modularity of RISC-V in Space

Journal Article (2019)
Authors

Stefano Di Mascio (Space Systems Egineering)

Alessandra Menicucci (Space Systems Egineering)

EKA Gill (TU Delft - Space Engineering)

Gianluca Furano (European Space Agency (ESA))

Claudio Monteleone (European Space Agency (ESA))

Affiliation
Space Systems Egineering
Copyright
© 2019 S. Di Mascio, A. Menicucci, E.K.A. Gill, Gianluca Furano, Claudio Monteleone
To reference this document use:
https://doi.org/10.2514/1.I010735
More Info
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Publication Year
2019
Language
English
Copyright
© 2019 S. Di Mascio, A. Menicucci, E.K.A. Gill, Gianluca Furano, Claudio Monteleone
Affiliation
Space Systems Egineering
Issue number
11
Volume number
16
Pages (from-to)
454-472
DOI:
https://doi.org/10.2514/1.I010735
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Abstract

This paper proposes a roadmap to address present and future needs in space systemswithRISC-Vprocessors. RISCVis an open and modular instruction set architecture, which is rapidly growing in popularity in terrestrial applications. To satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) low-area/low-power microcontrollers, 2) on-board computers, 3) general-purpose processors for payloads, and 4) enhanced payload processors for artificial intelligence. Several solutions based onRISCVare proposed for eachof these types of processors and comparedwith proprietary commercial-off-the-shelf andspacegrade solutions. An extensive analysis of the results available fromliterature is conducted to show that RISC-V has the potential to solve such a wide range of needs. This paper will also show the unprecedented number of open-source implementations and models that were developed in a relative short time on a single instruction set architecture. Future space systemscouldbenefit frommanyof those developments, andthisworkidentifies andhighlightswhat is stillmissing to satisfy the specific needs of processors for space, especially in terms of fault tolerance and technology readiness level.

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