This paper describes the work carried out to extend the NOEL-V platform to include data-level parallelism (DLP) by implementing an integer subset of the RISC-V Vector Extension. The performance and resource utilization efficiency of the resulting vector processor for different levels of DLP (i.e., number of lanes) have been compared to the baseline scalar processor on a Xilinx Kintex Ultrascale field-programmable gate array, employing typical kernels for compute-intensive applications. The role of the memory subsystem has also been investigated, comparing the results obtained with a low-latency and a high-latency main memory. The results show that the speed-up due to the use of the vector pipeline increases with the number of lanes in the vector processor, achieving up to 23.0× the performance of the scalar processor with only 4.3× the resources of the baseline scalar processor. Using an implementation with 32 lanes increases performance even for problem sizes larger than the number of lanes, achieving up to more than 11.7× the performance of the scalar processor with just 1.9× its resource utilization for 128 × 128 matrix multiplications. This work proves that implementations of the selected subset are easily scalable and fit for small-processor implementations in highly constrained space embedded systems.

This chapter provides an overview of the command and data handling system (CDHS) in small satellites and CubeSats. The chapter presents first analysis of radiation effects, specifically targeted at this subsystem, to justify components and architecture choices. Improvements in radiation testing strategies are also presented, specifically for small satellites. State-of-the-art components are then presented, providing an overview of the current market and the most common architectures. An overview of past and current missions is also presented, providing a clear mapping of the presented state-of-the-art components and architectures to guide future designs. High-level design considerations are also presented to help the reader follow some of the current trends in the sector. This chapter, overall, aims at presenting the most common approaches for the CDHS system and comparing this with traditional satellites, showing where the main differences lay with component selection and testing strategies being the fundamental points driving the architecture choices.

This paper evaluates the Single Event Upset (SEU) susceptibility of the NOEL-V processor, a novel and highly modular Intellectual Property (IP) Core by Cobham Gaisler on the Xilinx Kintex Ultrascale SRAM FPGA. The processor is based on the promising RISC-V architecture, an open source Instruction Set Architecture (ISA) that is quickly rising in popularity. In order to characterize the performance of the NOEL-V IP Core in the space radiation environment, the KCU105 development board is used as Device Under Test (DUT) and irradiated with medium and high energy protons. Thanks to the NOEL-V configurability, several versions of the NOEL-V were tested and microarchitectural differences could be exposed. The biggest influence on user logic upsets is observed to be related to the use of an operating system. For a single-core, high-performance configuration, a foreseen in-orbit failure rate of one failure every 395 days is found for for a 51.6° circular orbit at 420 km altitude. Findings indicate that the NOEL-V processor, with the implementation of targeted fault tolerant measures, can be a viable choice for space missions even as soft-core in SRAM FPGA. Due to its modularity, the processor can be used for a multitude of mission types ranging from high performance general-purpose to low-end microcontroller applications. Error Detection And Correction, which is not available in open source versions, will be needed to protect user memory and make sure upsets in caches and Configuration RAM (CRAM) do not lead to a failure of the processor.

Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.

Soft errors in embedded systems' memories like single-event upsets and multiple-bit upsets lead to data and instruction corruption. Therefore, devices deployed in harsh environments, such as space, use fault-tolerant processors or redundancy methods to ensure critical application dependability. Another rising concern in secure, critical space applications is the possible introduction of hardware Trojans in an untrusted phase of the manufacturing process. Besides environmental side-effects, an adversary that has injected a malicious mechanism e.g., in the processor or memory can trigger unwanted behavior or leak sensitive information. Techniques to prevent or mitigate hardware Trojans are important to ensure hardware security. Leveraging the openness of the RISC-V ISA, this paper introduces a novel solution to improve the security and dependability of softcores with a low area and latency overhead. The instruction validator which is the first part of this solution can effectively detect hardware Trojans and multiple-bit upsets in the instruction memory by checking instruction/address pairs using a Bloom filter probabilistic data structure. The second part of the solution is the proposal of an error correction code instruction memory using Hamming single-error correction to detect and correct single-event upsets. It has also been proven that the Hamming decoder improves the detection performance of the instruction validator.

The use of deep neural networks (DNNs) in terrestrial applications went from niche to widespread in a few years, thanks to relatively inexpensive hardware for both training and inference, and large datasets available. The applicability of this paradigm to space systems, where both large datasets and inexpensive hardware are not readily available, is more difficult and thus still rare. This paper analyzes the impact of DNNs on the system-level capabilities of space systems in terms of on-board decision making (OBDM) and identifies the specific criticalities of deploying DNNs on satellites. The workload of DNNs for on-board image and telemetry analysis is analyzed, and the results are used to drive the preliminary design of a RISC-V vector processor to be employed as a generic platform to enable energy-efficient OBDM for both payload and platform applications. The design of the memory subsystem is carried out in detail to allow full exploitation of the computational resources in typically resource-constrained space systems.

This paper discusses principles and techniques to evaluate processors for dependable computing in space applications. The focus is on soft errors, which dominate the failure rate of processors in space. Error, failure and propagation models from literature are selected and employed to estimate the failure rate due to soft errors in typical processor designs. A similar approach can be followed for applications with different radiation environments (e.g. automotive, servers, experimental instrumentation exposed to radiation on ground), by adapting the error models. This detailed white-box analysis is possible only for open-source Intellectual Property (IP) cores and in this work it will be applied to several open-source IP cores based on the RISC-V Instruction Set Architecture (ISA). For these case studies, several types of redundancy described in literature for space processors will be evaluated in terms of their cost-effectiveness and expected final in-orbit behavior. This work provides a comprehensive framework to assess efficacy and cost-effectiveness of redundancy, instead of listing and categorizing the techniques described in literature without assessing their relevance to state-of-the-art designs in space applications.

A new methodology for Total Ionizing Dose (TID) tests is proposed. It is based on the employment of an on-chip ⁹⁰ Sr/ ⁹⁰ Y beta source as alternative to standard methods such as ⁶⁰ Co gamma rays and electrons from LINAC. The use of a compact beta source for TID tests has several advantages. In particular, the irradiation of devices with more than one radiation source results in a better representation of the complex space radiation environment composed of several types, energies and dose-rates. In addition, the use of an easy handling beta source allows the irradiation of electronic devices without any damage to other auxiliary circuit. In this work, ⁹⁰ Sr/ ⁹⁰ Y beta source dosimetry and related radiation field characteristics are discussed in depth. In order to validate the proposed source for TID tests, a rather complex device such as the “SPC56EL70L5” microcontroller from ST-Microelectronics was exposed to ⁹⁰ Sr/ ⁹⁰ Y beta rays. The results of this test were compared to that of a previous test of another sample from the same lot with a standard gamma ⁶⁰ Co source. The electronic performances following the two irradiations have been found to be in excellent agreement, by demonstrating therefore the validity of the proposed beta source for TID tests.

This paper analyzes the contribution of caches to failures at processor level due to soft errors. In order to do this, approximated methodologies to estimate the percentage of the total Sensitive Area (SA) of a processor for each unit during early design exploration are proposed. Then, to identify the most vulnerable units, a metric called Relative Soft Error Vulnerability (RSEV) is defined. The analysis shows that caches are the most vulnerable units of state-of-the-art processors and that, even when considering higher-frequency and more complex pipelines representative of next-generation processors for space applications, the final in-orbit failure rate is dominated by failures caused by upsets in cache arrays. Even when protecting memory arrays with information redundancy, the large fraction of upsets occurring in caches is potentially the biggest threat to processor availability and reliability, especially if errors are modelled with invalid assumptions and are not properly handled when detected.

This paper presents preliminary position on the use of the novel, free and open RISC-V Instruction Set Architecture (ISA) for on-board electronics in space. The modular nature of this ISA, the availability of a rich software ecosystem, a rapidly growing community and a pool of open-source IP cores will allow Space Industry to spin-in developments from terrestrial fields (in terms of security, artificial intelligence, support for operating systems, hardware acceleration etc.) while focusing its efforts mainly on aspects related to the specific needs of on-board electronics for space applications (e.g. fault tolerance, observability, error signaling, etc.). This will improve reuse and avoid the necessity of developments from scratch when not strategically needed, eventually increasing productivity and reducing costs. The use of an open, non proprietary ISA will allow ad-hoc design of microarchitecture-level soft error countermeasures that can greatly increase the robustness of Application Specific Standard Products (ASSP) and FPGA implementations.