A European Roadmap to Leverage RISC-V in Space Applications

Conference Paper (2022)
Author(s)

Gianluca Furano (European Space Agency (ESA))

S. Di Mascio (TU Delft - Space Systems Egineering)

A. Menicucci (TU Delft - Space Systems Egineering)

Claudio Monteleone (European Space Agency (ESA))

Space Systems Egineering
Copyright
© 2022 Gianluca Furano, S. Di Mascio, A. Menicucci, Claudio Monteleone
DOI related publication
https://doi.org/10.1109/AERO53065.2022.9843361
More Info
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Publication Year
2022
Language
English
Copyright
© 2022 Gianluca Furano, S. Di Mascio, A. Menicucci, Claudio Monteleone
Space Systems Egineering
Bibliographical Note
Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public. @en
ISBN (print)
978-1-6654-3760-8
Reuse Rights

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Abstract

RISC-V is an open and modular Instruction Set Architecture(ISA) which is rapidly growing in popularity in terrestrial applications. This paper presents the place in future space embedded systems ESA's roadmap for RISC-V based processors. In order to satisfy different applications with contrasting requirements in satellite data systems, four different types of processors are identified: 1) General-Purpose (GP) processors for payloads 2) main platform On-Board Computers (OBCs) controllers 3) low-area/low-power microcontrollers (uCs), 4) enhanced payload processors with support for Artificial Intelligence (AI). We also describe the state of the art of the RISC-V software ecosystem, including the currently available hardware platforms, with a focus on developments for space applications and what has already been done in the European Space Industry. Finally, planned activities are presented, with a focus on the role of the European ecosystem.

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