Is RISC-V ready for Space? A Security Perspective
Luca Cassano (Politecnico di Milano)
Stefano Di Mascio (TU Delft - Aerospace Engineering)
Alessandro Palumbo (University of Rome Tor Vergata)
Alessandra Menicucci (TU Delft - Aerospace Engineering)
Gianluca Furano (European Space Agency (ESA))
Giuseppe Bianchi (University of Rome Tor Vergata)
Marco Ottavi (University of Rome Tor Vergata, University of Twente)
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Abstract
Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w.r.t. performance. On the other hand, this design paradigm exposes the system to a number of security threats both at design-time and at runtime. In this paper, we discuss the security issues related to space applications mainly focusing on threats that come from the adoption of the well-known RISCV microprocessor. We highlight how Hardware Trojan horses (HTHs) and Microarchitectural Side-Channel Attacks (MSCAs) may compromise the overall system operation by either altering its nominal behavior or by stealing secret information. We discuss the security extensions provided by the RISC-V architecture as well as their limitations. The paper is concluded by an overview of the issues that are still open regarding the security of such microprocessor in the space domain.