A 40 nm integrated cryo-CMOS 120 MHz switching power converter for power management at 4 K aiming large-scale quantum computers

Conference Paper (2026)
Author(s)

Xavier Iniguez Faine (Universitat Politécnica de Catalunya)

Eduard Alarcon (Universitat Politécnica de Catalunya)

Fabio Sebastiano (TU Delft - QCD/Sebastiano Lab, TU Delft - Electrical Engineering, Mathematics and Computer Science, TU Delft - QuTech Advanced Research Centre)

Llorenc Fanals-I-Batllori (Stanford University)

Aldo Pena Perez (Stanford University)

Research Group
Quantum Circuit Architectures and Technology
DOI related publication
https://doi.org/10.1109/ISCAS66217.2026.11562983 Final published version
More Info
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Publication Year
2026
Language
English
Research Group
Quantum Circuit Architectures and Technology
Pages (from-to)
2505-2509
Publisher
IEEE
ISBN (electronic)
9798331577698
Event
2026 IEEE International Symposium on Circuits and Systems, ISCAS 2026 (2026-05-24 - 2026-05-27), Shanghai, China
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Abstract

Quantum computers require a complex cryogenic electrical interface to avoid the wiring bottleneck between the cryogenic qubits and the room-temperature controllers. Such cryogenic electronics are typically supplied through long cables that introduce significant resistive and thermal losses, hindering efficiency and scalability. To circumvent this hurdle, this work presents a fully integrated cryo-CMOS synchronous buck converter operating at 4 K that enables the use of a high-voltage low-current supply to reduce resistive losses in the cables. Implemented in 40 nm CMOS, the converter targets a 7 V input, a 1.1 V output, and load currents of 100-300 mA, while achieving 63% efficiency by exploiting the cryogenic behavior of active and passive CMOS devices. These results pave the way for the power-management systems required in the cryo-CMOS SoC controlling future large-scale quantum computers.

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