Towards Ultra-Low-Voltage and Ultra-Low-Power Discrete-Time Receivers for Internet-of-Things

Conference Paper (2018)
Author(s)

Feng Wei Kuo (Taiwan Semiconductor Manufacturing Company (TSMC))

Sandro Binsfeld Ferreira (Unisinos University)

Ron Chen (Taiwan Semiconductor Manufacturing Company (TSMC))

Lan Chou Cho (Taiwan Semiconductor Manufacturing Company (TSMC))

Chewn-Pu Jou (Taiwan Semiconductor Manufacturing Company (TSMC))

Mark Chen (Taiwan Semiconductor Manufacturing Company (TSMC))

Masoud Babaie (TU Delft - Electronics)

Robert Bogdan Staszewski (University College Dublin)

Research Group
Electronics
DOI related publication
https://doi.org/10.1109/MWSYM.2018.8439369
More Info
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Publication Year
2018
Language
English
Research Group
Electronics
Article number
8439369
Pages (from-to)
1211-1214
ISBN (print)
978-1-5386-5068-4
ISBN (electronic)
978-1-5386-5067-7
Event
2018 IEEE/MTT-S International Microwave Symposium, IMS 2018 (2018-06-10 - 2018-06-15), Philadelphia, United States
Downloads counter
237

Abstract

In this paper, we investigate an impact of voltage supply scaling on power consumption and performance of a new class of wireless receivers (RX) for Internet-of-Things (IoT) applications: a discrete-time (DT) superheterodyne architecture realized in nanoscale CMOS using inverter-based gm and switched capacitors. The power supply is partitioned into three separate domains: RF, intermediate frequency (IF) processing, and clocking, which allows them to be independently regulated to assess their respective impact. The DT-RX maintains its functionality, albeit with some acceptable loss of performance, when the core supplies are varied by as much as an octave, i.e., from the nominal 1.1 V down to 0.55V. The DT-RX IC is then connected to a switched-capacitor based voltage doubler array on a companion IC die such that the DT-RX can be powered at the octave range of 0.275-0.55 V from an energy harvester. The sensitivity at the doubler's 0.275/0.55 V input is -85/-95 dBm while consuming 1.0/2.4mW. Both ICs are implemented in TSMC 28-nm LP CMOS.

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