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A matrix-multiply unit for posits in reconfigurable logic leveraging (Open)CAPI

Conference Paper (2018)
Author(s)

Jianyu Chen (Student TU Delft)

Zaid Al-Ars (TU Delft - Electrical Engineering, Mathematics and Computer Science)

H. Peter Hofstee (IBM Research, TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.1145/3190339.3190340 Final published version
More Info
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Publication Year
2018
Language
English
Research Group
Computer Engineering
Article number
1
Pages (from-to)
1-5
ISBN (electronic)
978-1-4503-6414-0
Event
CoNGA 2018 (2018-03-28 - 2018-03-28), Singapore, Singapore
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218
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Abstract

In this paper, we present the design in reconfigurable logic of a matrix multiplier for matrices of 32-bit posit numbers with es=2 [1]. Vector dot products are computed without intermediate rounding as suggested by the proposed posit standard to maximally retain precision. An initial implementation targets the CAPI 1.0 interface on the POWER8 processor and achieves about 10Gpops (Giga posit operations per second). Follow-on implementations targeting CAPI 2.0 and OpenCAPI 3.0 on POWER9 are expected to achieve up to 64Gpops. Our design is available under a permissive open source license at https://github.com/ChenJianyunp/Unum_matrix_multiplier. We hope the current work, which works on CAPI 1.0, along with future community contributions, will help enable a more extensive exploration of this proposed new format.