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An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs

Journal Article (2018)
Author(s)

Feng-Wei Kuo (Taiwan Semiconductor Manufacturing Company (TSMC))

Masoud Babaie (TU Delft - Electronics)

Huan-Neng (Ron) Chen (Taiwan Semiconductor Manufacturing Company (TSMC))

Lan-Chou Cho (Taiwan Semiconductor Manufacturing Company (TSMC))

Chewn-Pu Jou (Taiwan Semiconductor Manufacturing Company (TSMC))

Mark Chen (Taiwan Semiconductor Manufacturing Company (TSMC))

Bogdan Staszewski (TU Delft - Electronics)

Research Group
Electronics
DOI related publication
https://doi.org/10.1109/TCSI.2018.2855972
More Info
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Publication Year
2018
Language
English
Research Group
Electronics
Issue number
11
Volume number
65
Pages (from-to)
3756-3768
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Abstract

We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as wide tuning range, and fine-resolution class-F digitally controlled oscillator (DCO) with only switchable metal capacitors. The 0.4-mW TDC clocked at 40 MHz maintains 7-ps resolution for <-107 dBc/Hz in-band phase noise while the 7.3-mW DCO emits -157 dBc/Hz at 20 MHz offset at 2 GHz. Reference spurs are <-91 dBc, while fractional spurs are <-55 dBc. The ADPLL supports a 2-point modulation and consumes 11.5-mW while occupying 0.22 mm$^2$.