Specification and Implementation of a DMA Controller in an Embedded System

Abstract

The fast growing of In-Car entertainment application leads to an increasing challenge for both data computation and data communication, which are managed by the microprocessor. The thesis project is the third stage of a continuous Direct Memory Access(DMA) Controller project in NXP Semiconductors for the purpose of specifying and implementing a DMA Controller to take over data communication tasks from the microprocessor. In the first step of the thesis, a test principle was investigated to fully test the existing results, but the simulation results of the Core Unit did not satisfy the requirements. The Core Unit of the DMA Controller is responsible for the sequential-single transfer and burst transfer involving wait states. The existing specification and implementation were analyzed, and a number of possible approaches for improvements were identified. During the second step, the Core Unit was re-specified according to these approaches, and fully implemented using VHDL to fulfill the requirements. After the Core Unit design, the functions of Linked List transfer was specified with Hatley and Pirbhai methodology. The Linked List Unit, which manages the Linked List transfer, was specified to support both the Static and Dynamic Linked List transfer. This specification provides an essential base for the future implementation. The implementation of the Core Unit was tested with Simvision following the proposed test principle. The results satisfied the function requirements. Thus, the specification was proved to be feasible. Additionally, the Core Unit was synthesized using Cadence Ambit. The number of the equivalent gates of a Core Unit Cell is 3k, which is smaller than the currently used DMA Controller in NXP Semiconductors.