A 6.3 μW 20 bit Incremental Zoom-ADC with 6 ppm INL and 1 μV Offset

Journal Article (2013)
Authors

Y. Chae (Yonsei University)

K. Souri (TU Delft - Electronic Instrumentation)

K. A.A. Makinwa (TU Delft - Electronic Instrumentation)

Research Group
Electronic Instrumentation
Copyright
© 2013 Y. Chae, K. Souri, K.A.A. Makinwa
To reference this document use:
https://doi.org/10.1109/JSSC.2013.2278737
More Info
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Publication Year
2013
Language
English
Copyright
© 2013 Y. Chae, K. Souri, K.A.A. Makinwa
Research Group
Electronic Instrumentation
Bibliographical Note
Accepted Author Manuscript@en
Issue number
12
Volume number
48
Pages (from-to)
3019-3027
DOI:
https://doi.org/10.1109/JSSC.2013.2278737
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Abstract

A 20-bit incremental ADC for battery-powered sensor applications is presented. It is based on an energy-efficient zoom ADC architecture, which employs a coarse 6-bit SAR conversion followed by a fine 15-bit ΔΣ conversion. To further improve its energy efficiency, the ADC employs integrators based on cascoded dynamic inverters for extra gain and PVT tolerance. Dynamic error correction techniques such as auto-zeroing, chopping and dynamic element matching are used to achieve both low offset and high linearity. Measurements show that the ADC achieves 20-bit resolution, 6 ppm INL and 1 μV offset in a conversion time
of 40 ms, while drawing only 3.5 μA current from a 1.8 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 182.7 dB. The 0.35 mm² chip was fabricated in a standard 0.16 μm CMOS process.

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