Reduction of Power Consumption in Hybrid Beamforming Integrated Circuits Using Amplitude Taper Grouping

Abstract

A novel system design framework is proposed for hybrid beamforming receivers to reduce the power consumption withoutany loss in sensitivity or beam scanning performance. Only the amplitude taper that corresponds to the relative individual analog subarrays is applied in the analog beamforming domain, while the rest of the taper is applied using digital beamformingcoefficients. Based on a given array size, number of beams, and the desired sidelobe suppression level, the number of analog subarrays and the beamforming integrated circuit (BFIC) component characteristics are optimally selected. An improved BFIC module is recommended that has less analog pre-amplification and a smaller dynamic range of variable attenuator steps. For concept demonstration, a benchmark analog beamforming and hybrid beamforming SatCom architecture, without this improvement, are simulated using a joint signal and power consumption analysis. For a 32 × 32 element array with 2 simultaneous beams and 30 dB side lobe tapering, the analog benchmark and hybrid benchmark (with 64 subarrays) are simulated to have a power consumption of 50.1 W and 66.5 W, respectively, A similar hybrid beamforming architecture with modified BFIC modules is shown to have a total power consumption of 40.3 W, less than both benchmarks. Furthermore, a comprehensive analysis of the system is conducted to illustrate how power consumption is influenced by the chosen number of subarrays with respect to the targeted sidelobe suppression, array size, number of beams and number of ADC bits.