High-Fidelity Controlled- Z Gate with Maximal Intermediate Leakage Operating at the Speed Limit in a Superconducting Quantum Processor
V. Negîrneac (Lisbon Technical University, TU Delft - BUS/Quantum Delft)
H. Ali (Kavli institute of nanoscience Delft, TU Delft - QCD/DiCarlo Lab)
N. Muthusubramanian (TU Delft - QCD/DiCarlo Lab, Kavli institute of nanoscience Delft)
F. Battistel (TU Delft - QCD/Terhal Group)
R.E. Sagastizabal (TU Delft - QCD/DiCarlo Lab, Kavli institute of nanoscience Delft)
M. S. Moreira (Kavli institute of nanoscience Delft)
Jorge Marques (Kavli institute of nanoscience Delft, TU Delft - QCD/DiCarlo Lab)
W.J. Vlothuizen (TU Delft - BUS/TNO STAFF, TNO)
M.C. Beekman (TNO, TU Delft - BUS/TNO STAFF)
C. Zachariadis (TU Delft - QCD/DiCarlo Lab, Kavli institute of nanoscience Delft)
Nadia Haider (TU Delft - BUS/TNO STAFF, TNO)
A. Bruno (TU Delft - QCD/DiCarlo Lab, Kavli institute of nanoscience Delft)
Leonardo di Carlo (Kavli institute of nanoscience Delft, TU Delft - QCD/DiCarlo Lab, TU Delft - QN/DiCarlo Lab)
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Abstract
Simple tuneup of fast two-qubit gates is essential for the scaling of quantum processors. We introduce the sudden variant (SNZ) of the net zero scheme realizing controlled-Z (CZ) gates by flux control of transmon frequency. SNZ CZ gates realized in a multitransmon processor operate at the speed limit of transverse coupling between computational and noncomputational states by maximizing intermediate leakage. Beyond speed, the key advantage of SNZ is tuneup simplicity, owing to the regular structure of conditional phase and leakage as a function of two control parameters. SNZ is compatible with scalable schemes for quantum error correction and adaptable to generalized conditional-phase gates useful in intermediate-scale applications.