Design of a 4-bit RISC Processor in 2 μm Silicon Carbide CMOS Technology
J. Xu (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Sten Vollebregt – Mentor (TU Delft - Electronic Components, Technology and Materials)
Zhenhua Zhang – Graduation committee member (TU Delft - Electronic Components, Technology and Materials)
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Abstract
Silicon carbide (SiC) is a wide-bandgap semiconductor with excellent thermal stability, high breakdown voltage, and robustness under harsh environments, making it well-suited for high-temperature digital logic applications. Compared with conventional silicon, SiC devices maintain reliable operation at significantly higher temperatures due to their strong electric field tolerance and reduced leakage characteristics. However, as an emerging technology, its integration level for digital circuits is still in a preliminary stage and requires validation through a full chip design and fabrication process.
This thesis presents the design and simulation of a fully functional 4-bit RISC processor in a 2 µm SiC CMOS process developed by Fraunhofer IISB. The processor includes the implementation of the ALU, program counter, control unit, and memory blocks, together with validation of its functionality and performance through circuit-level simulations across a wide temperature range. Results demonstrate stable operation and robustness up to 500◦C, as well as reliable logic performance at clock frequencies up to 750 kHz. The work further establishes a foundation for future digital systems based on the Fraunhofer IISB SiC CMOS process, paving the way toward more complex architectures such as 16-bit processors for real-world harsh-environment applications.