Reconfigurable universal SAD-multiplier array

Conference paper (2005)

Authors

H Calderón Computer Engineering - EEMCS
S Vassiliadis Computer Engineering - EEMCS
Research Group
Computer Engineering (EEMCS) (TU Delft)
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Published Date

2005

Language

Undefined/Unknown

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

In this paper, we investigate the collapsing of some multi-operand addition related operations into a single array. More specifically we consider multiplication and Sum of Absolute Differences (SAD) and propose an array capable of performing the aforementioned operations for unsigned, signed magnitude, and two's complement notations. The array, called a universal array, is divided into common and controlled logic blocks intended to be reconfigured dynamically. The proposed unit was constructed a ...

Keywords: binary multiplication, partial reconfiguration, reconfigurable computing, sum of absolute differences