Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width

Journal article (2024)

Authors

Houcai Luo Chongqing University
Huan Wu Chongqing University
Jing-Ping Zhang Chongqing University
Bo-Feng Zheng Chongqing Pingchuang Institute of Semiconductors Company Ltd.
Lei Lang Chongqing University
Kouchi Zhang Electronic Components, Technology and Materials - EEMCS
Xian-Ping Chen Chongqing University
Research Group
Electronic Components, Technology and Materials (EEMCS) (TU Delft)
BJT Avalanche reliability Hexagonal cell topology SiC VDMOSFET UIS
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Published Date

2024

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Components, Technology and Materials

Abstract

The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L JFET=1.4μ m has the best HF-FOM (R on × Cgd) and HF-FOM (R on × Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.