Study on Characteristics and UIS of Hexagonal Planar SiC VDMOSFETs With Varied JFET Width
Hou-Cai Luo (Chongqing University)
Huan Wu (Chongqing University)
Jing-Ping Zhang (Chongqing University)
Bo-Feng Zheng (Chongqing Pingchuang Institute of Semiconductors Company Ltd.)
Lei Lang (Chongqing University)
Guo-Qi Zhang (TU Delft - Electronic Components, Technology and Materials)
Xian-Ping Chen (Chongqing University)
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Abstract
The hexagonal cell topology of planar SiC VDMOSFETs with varied JFET width (LJFET) are designed and manufactured in this study. L JFET=1.4μ m has the best HF-FOM (R on × Cgd) and HF-FOM (R on × Qgd) by comparing the dynamic and static parameters of each design. Besides, the UIS reliability and failure mechanism for series designs are investigated by experiment and TCAD simulation. The results show that the high temperature is generated by energy dissipation during avalanche and it drives the parasitic BJT conduction, causing Ids out of control and instantaneous heat concentration in a very short time. The extremely high temperature causes internal cracking of the material and metal melting, resulting in gate-source short circuit and device damage. It would provide suggestions for device design and reliability consideration.