Stochastic Resonance Analog-to-Digital Conversion

Abstract

Stochastic resonance (SR) is a phenomenon in which the presence of noise increases the performance of the system. The phenomenon has first been discovered in a climate change model and is later observed in neuronal systems. In artificial, electronic, systems, stochastic resonance is observed in systems based on Schmitt-Triggers and comparators. The common property of all these systems is the threshold, which, when reached, causes a large transition in the system. The presence of noise in small signals can cause the system to reach the threshold or can increase the number of state transitions, increasing the quality of the output signal. Oversampling and integration are applied to reconstruct the original signal. Biomedical signals are typically affected relative high noise levels. The observations of stochastic resonance in nature, such as biological neural systems, combined with the observations of stochastic resonance in comparator-based circuits formed the inspiration and fundamental of this thesis research. The goal of this project is to investigate the potentials for using stochastic resonance in biomedical signal acquisition. In this thesis, an explorative study on the behavior, the performance, and the design of an analog-to-digital (ADC) converter fully based on stochastic resonance in a 1-bit quantizer is presented. The design and application focus on processing ECG measurements. A comprehensive analysis of the behavior, and an analytical method to determine the performance of 1-bit stochastic resonance analog-to-digital conversion in a comparator based circuit is presented. A novel technique using a negative hysteresis is found, showing a potential increase in SNDR up to 6.4 dB. Based on this analysis, a system level design is presented which implements a closed-loop operation of the stochastic resonance ADC. This design comprises a feedback loop to control the noise level, realizing the maximum performance over an input amplitude range from 1-10 mV, independent from noise present in the system. Furthermore, an offset compensation scheme is presented, which controls the threshold of the comparator, and a digital multi-rate filter is implemented to filter the high frequency noise, and to apply downsampling the highspeed bitstream. IC implementation of the comparator and the noise source is studied. A low-offset
comparator, based on a strongARM latch, is proposed, with an offset calibration technique, reducing the offset to below 50 μV. The noise source creates a flat noise spectrum from 20 kHz to 4 MHz, using amplified thermal noise of a resistor combined with the amplifier noise. The proposed system can deliver a 27 dB SNDR in a signal bandwidth of 216 Hz, and an input amplitude range of 10×, using a sampling frequency of 2 MHz.