Efficient Methodology for ISO26262 Functional Safety Verification

Conference paper (2019)

Authors

F. Augusto da Silva Computer Engineering - EEMCS , Cadence Design Systems
Ahmet Cagri Bagbaba Cadence Design Systems
S. Hamdioui Quantum & Computer Engineering
Christian Sauer Cadence Design Systems
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2019 F. Augusto da Silva, Ahmet Cagri Bagbaba, S. Hamdioui, Christian Sauer
DOI
help_outline
https://doi.org/10.1109/IOLTS.2019.8854449
ATPG Formal Methods Functional Safety Fault Injection Simulation ISO26262
More Info
expand_more

Published Date

01-07-2019

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.