Efficient Methodology for ISO26262 Functional Safety Verification
F. Silva (TU Delft - Computer Engineering, Cadence Design Systems)
Ahmet Cagri Bagbaba (Cadence Design Systems)
S. Hamdioui (TU Delft - Quantum & Computer Engineering)
Christian Sauer (Cadence Design Systems)
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Abstract
Tolerance to random hardware failures, required by ISO26262, entails accurate design behavior analysis, complex Verification Environments and expensive Fault Injection campaigns. This paper proposes a methodology combining the strengths of Automatic Test Pattern Generators (ATPG), Formal Methods and Fault Injection Simulation to decrease the efforts of Functional Safety Verification. Our methodology results in a fast-deployed Fault Injection environment achieving Fault detection rates higher than 99% on the tested designs. In addition, ISO26262 Tool Confidence level is improved by a fault analysis report that allows verification of malfunctions in the outputs of the tools.