On Carving Basic Boolean Functions on Graphene Nanoribbons Conduction Maps

Abstract

As CMOS feature size approaches atomic dimensions, unjustifiable static power, reliability, and economic implications are exacerbating, prompting for research and development on new materials, devices, and/or computation paradigms. Within this context, Graphene Nanoribbons (GNRs), owing to graphene's excellent electronic properties, may serve as basic blocks for carbon-based nanoelectronics. En route to GNR-based logic circuits, the ability to externally control GNRs' conduction to map a basic Boolean logic function onto its electrical characteristics, with a high 1ON/1OFF ratio, and uncompromised carriers mobility, is the main desideratum. To this end, we augment a trapezoidal GNR with top gates as controlling inputs, and investigate its conductance G by means of the NEGF-Landauer formalism. Further, we demonstrate that the butterfly GNR can exhibit conduction maps (high G for logic “1”, and low G for logic “0”) capturing the functionality of 2 and 3-input Boolean gates, by properly adjusting its topology and dimensions. Our simulations prove butterfly GNR structure capability to capture basic Boolean logic transfer functions, while potentially providing 30× and 3000× smaller propagation delay and gate active area, respectively, when compared to 15 nm CMOS equivalent counterparts, establishing GNR's potential as basic building block for future graphene-based logic gates.