Efficient Memory Architecture for Next Generation Low-Power Embedded Systems
S. Mohapatra (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Vito Kortbeek (TU Delft - Embedded Systems)
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Abstract
In this thesis we propose a novel memory architecture design that is robust to frequent memory failures targeting next generation low power embedded system. We explore the how the architecture works and perform detailed evaluations to show that our system achieves better performance than the state-of-the-art.