Efficient Memory Architecture for Next Generation Low-Power Embedded Systems

Master thesis (2022)

Authors

S. Mohapatra Electrical Engineering, Mathematics and Computer Science

Contributors

V. Kortbeek Embedded Systems - (supervisor 1)

Przemysław Pawełczak Embedded Systems - (supervisor 2)

Faculty

Electrical Engineering, Mathematics and Computer Science

More Info

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Published Date

26-08-2022

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

In this thesis we propose a novel memory architecture design that is robust to frequent memory failures targeting next generation low power embedded system. We explore the how the architecture works and perform detailed evaluations to show that our system achieves better performance than the state-of-the-art.