A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling

Journal article (2017)

Authors

Kristof Blutman NXP Semiconductors
Ajay Kapoor NXP Semiconductors
Arjun Majumdar NXP Semiconductors
Jacinto Garcia Martinez NXP Semiconductors
Juan Echeverri NXP Semiconductors
Leo Sevat NXP Semiconductors
Arnoud P. van der Wel NXP Semiconductors
H Fatemi NXP Semiconductors
K.A.A. Makinwa Microelectronics
Department
Microelectronics
Copyright: © 2017 Kristof Blutman, Ajay Kapoor, Arjun Majumdar, Jacinto Garcia Martinez, Juan Echeverri, Leo Sevat, Arnoud P. van der Wel, Hamed Fatemi, K.A.A. Makinwa
DOI
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https://doi.org/10.1109/JSSC.2016.2637003
Power management Voltage stacking Charge recycling Level shifter Balanced voltage islands Microcontrollers Switched capacitor regulators
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Published Date

2017

Language

English

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Department

Microelectronics

Abstract

A 40-nm microcontroller featuring voltage stacked memory and logic is presented. This involved connecting the power domains of the memory and logic in series, such that the ground of one power domain is connected to the positive supply rail of the other. In this paper, an ARM Cortex-M0+ and its peripherals are powered from 0 V to VDD, while its 4-kB ROM and the 16-kB SRAM are powered from VDD to 2 VDD. Since the memory and logic will, in general, draw different supply currents, the midrail VDD is provided by an on-chip switched capacitor voltage regulator (SCVR). To allow a direct comparison of voltage stacking with a conventional single supply, it can be turned off by configuring the SCVR to power both the memory and logic from 0 V and VDD. Turning on voltage stacking results in 96% power conversion efficiency, while the active converter area is reduced by 2.6 ×. Despite the use of a smaller SCVR, the voltage stacking reduces the supply noise by 3.4 dB and the output voltage drops from 58 to 36 mV.