Reduced Calibration Error Employing Parametrized EM models and DC Load Extraction

Conference paper (2023)

Authors

E. Shokrolahzade Electronics - EEMCS
C. De Martino Vertigo Technologies
M. Spirito Electronics - EEMCS
Research Group
Electronics (EEMCS) (TU Delft)
Copyright: © 2023 E. Shokrolahzade, C. De Martino, M. Spirito
DOI: https://doi.org/10.1109/ARFTG56062.2023.10148882
Calibration On-wafer Quartz Vector Network Analyzer Probe-level Short Open Load Reciprocal SOLR
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Published Date

2023

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronics

Abstract

In this contribution we present an approach to reduce the error arising from the variations of the lumped load, due to process spread, in probe level calibrations. First, full-wave electromagnetic (EM) simulations are employed to generate the nominal standard responses, then a parametric EM simulation of the load structure is used to generate a parametrized model of the standard. The approach is tested using a Short-Open-Load-Reciprocal calibration algorithm and an impedance standard calibration substrates developed on a 150 mm Quartz wafer (400 pm thick). In this process the high fidelity of the lateral dimension of the fabricated structures, realized using IC Photolithography, allows to confine the variations of the load response to only the thin-film resistor thickness spread. The DC response of the load, measured during the calibration step, is used to identify the specific RF response of the probed load from the parametric model. A complete analysis using full-wave EM simulations accounting for process variation is presented together with a set of experimental data up to 67GHz.