Electronic implants are becoming a valuable tool to explore and regulate neural activity, potentially overcoming neural disabilities that are still incurable. On the one hand, neural recording can provide tremendous insight into the neural system and the sometimes accompanied neural diseases. On the other hand, neural stimulation is necessary to control or adjust neural activity related to neural diseases. Detail of neural recording and stimulation is achieved with highly dense and often deep implantable electrodes (spatial resolution), while neural patterns are found with larger neural area coverage. In both stimulating and recording, a combination of spatial resolution and area coverage can be key to understanding and curing. Application-specific integrated circuits (ASICs) are often employed for the interaction with the electrodes interfacing with neural tissue but ASICs are limited in size, which consequently limits the amount of individual recording or stimulation channels. The de facto solution to circumvent this limitation is to multiplex high numbers of electrodes to a single ASIC channel. However, due to switching and signal latencies only a limited number of electrodes can be multiplexed per channel. Multiple channels on an ASIC are therefore desirable nonetheless to accommodate implants with a many electrodes. Due to recent miniaturization advances, an ever-increasing number of channels can be made available on a single ASIC and the urgency arises to investigate connecting and integrating these channels to electrodes on a flexible implantable substrate. In this work we will investigate technology for assembling a fully flexible electrode array substrate to an ASIC with a high number of channels. For such assemblies, a routing optimiser was developed especially for flexible implants, optimising for chip size and critical substrate limitations. However, with no established manufacturing methodology for such systems, technology parameters were not fully understood. Therefore, initial efforts were put into fabrication of a custom chip with which 72 chip-to-substrate gold stud contacts can be evaluated by means of 4-point measurements and daisy-chaining. This multifunctional chip allows for experiments at various chip-to-substrate contact diameters and pitches. In addition, different materials, including polycarbonate (PC), polyimide (PI) and thermoplastic polyurethane (TPU) were investigated as candidate substrate materials. A transfer methodology, using copper and FR-4 as carrier materials, proved fruitful for these polymeric materials. TPU samples showed particularly promising results, with the main advantage that it can encapsulate the entire implantable system, including chip and metallization, without the formation of additional material interfaces. This has significant advantages for the longevity of implantable systems. A second chip iteration with similar functionality was manufactured with 1008 gold electroplated contacts. The chip measures at 4x4mm² and contacts were designed to be 36x36µm² in size, pitched at 80µm apart. Contact resistances of this chip on TPU substrates were in the range of 5.5 and 73mΩ but the yield of proper contact dropped from 100% to an estimated 90% compared to experiments with the previous chip. A demonstrator product, fully embedded in TPU, was made using the same chip and connects 324 peripheral electrodes to the chip on a single Au metallization layer.