Print Email Facebook Twitter Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter Title Analysis and Design of a High-Order Discrete-Time Passive IIR Low-Pass Filter Author Tohidian, M. Madadi, I. Staszewski, R.B. Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics Date 2014-10-13 Abstract In this paper, we propose a discrete-time IIR low-pass filter that achieves a high-order of filtering through a charge-sharing rotation. Its sampling rate is then multiplied through pipelining. The first stage of the filter can operate in either a voltage-sampling or charge-sampling mode. It uses switches, capacitors and a simple gm-cell, rather than opamps, thus being compatible with digital nanoscale technology. In the voltage-sampling mode, the gm-cell is bypassed so the filter is fully passive. A 7th-order filter prototype operating at 800 MS/s sampling rate is implemented in TSMC 65 nm CMOS. Bandwidth of this filter is programmable between 400 kHz to 30 MHz with 100 dB maximum stop-band rejection. Its IIP3 is +21 dBm and the averaged spot noise is 4.57 nV/$surd$ Hz. It consumes 2 mW at 1.2 V and occupies 0.42 mm 2. Subject CMOSIIRdigital equalizationdiscrete timehigh linearityhigh orderlow noiselow powerlow-pass filterpassivereal polereconfigurableswitched capacitor To reference this document use: http://resolver.tudelft.nl/uuid:4d8edade-51d8-479d-96c1-18244e2eb6d8 DOI https://doi.org/10.1109/JSSC.2014.2359656 Publisher IEEE ISSN 0018-9200 Source IEEE Journal of Solid-State Circuits, 49 (11), 2014 Part of collection Institutional Repository Document type journal article Rights © 2014 IEEE Files PDF Tohidian_2014.pdf 3.24 MB Close viewer /islandora/object/uuid:4d8edade-51d8-479d-96c1-18244e2eb6d8/datastream/OBJ/view