Print Email Facebook Twitter Test Set Development for Cache Memory in Modern Microprocessors Title Test Set Development for Cache Memory in Modern Microprocessors Author Al-Ars, Z. Hamdioui, S. Gaydadjiev, G. Vassiliadis, S. Faculty Electrical Engineering, Mathematics and Computer Science Department Microelectronics & Computer Engineering Date 2008-06-08 Abstract Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transistors dedicated to such memories. This paper discusses the methodology used to develop effective and efficient cache tests, and the way it is implemented to optimize the test set used at Intel to test their 512-kB caches manufactured in a 0.13- mtechnology. An example is shown where a maximal test set of 15 tests with a corresponding maximum test time of 160.942 ms/chip is optimized to only six tests that require a test time of only 30.498 ms/chip. Subject fault coveragememory testingmicroprocessor cachetest set developmenttest time To reference this document use: http://resolver.tudelft.nl/uuid:7fc93845-cd3a-4339-90e1-6411fe183d67 Publisher IEEE ISSN 1063-8210 Source IEEE Transactions on Very Large Scale Integration, 16 (6), 2008 Part of collection Institutional Repository Document type journal article Rights (c) 2008 IEEE Files PDF al-ars2008.pdf 801.83 KB Close viewer /islandora/object/uuid:7fc93845-cd3a-4339-90e1-6411fe183d67/datastream/OBJ/view