A 10-b 330nW Third-Order Predictive SAR ADC Dedicated to Neural Recording Brain Implants

Abstract

This paper reports on a predictive analog-todigital converter (ADC). The proposed ADC employs a linear predictive filter to prepare a prediction for the current sample based on the values of the previous digital codes. This leads to significant reduction in the mean bit cycle of the converter. It is shown in this work that this idea is significantly more effective for the digitization of biological signals (e.g., intra-cortical neural signals). Compared with other similar techniques available in the literature, the proposed predictive ADC is significantly more successful for small signal-to-noise ratios. The proposed algorithm results in 48% and 37% reduction in the converter’s mean bit cycle compared with the conventional and LSB-first structures, respectively. Designed and post-layout simulated in a 90-nm standard CMOS technology and operated at 200 kS/s with a supply voltage of 0.4 V, the 10-bit predictive ADC consumes 330 nW. The circuit occupies a core area of 0.025 mm2, achieves an ENOB of 9.42 bits, a figure-of-merit of 2.4 fJ/conv.-step, and an SFDR of 65.8 dB. The DNL and INL of the circuit are within 0.45 LSB and 0.56 LSB, respectively.