Implementation of the DAC is usually the bottleneck in designing a SAR ADC. Here an innovative DAC-less SAR (DLSAR) ADC architecture is presented which alleviates some drawbacks of the conventional SAR counterpart. The proposed DLSAR binary search algorithm is comprised of two arithmetic operations of division-by-two and subtraction to emulate the DAC function. The hardware of the DLSAR ADC is implemented using ordinary circuit building blocks of a SAR ADC but with less complexity and more robustness against PVT variations as DAC is removed. The developed DLSAR architecture is versatile so that the converter hardware could be readily reconfigured for different sampling rates and resolutions. Based on post-layout simulations in 0.18 μm CMOS process, the designed 8-bit DLSAR ADC consumes 150 μW of power at 2 MS/s including the asynchronous control logic circuit. The SFDR of the converter is up to 62 dB and the ENOB reaches 7.8 bits while it remains above 7.5 bits across most PVT corners without calibration. Also, by reconfiguring the DLSAR ADC to 9-bit resolution at 1 MS/s, the ENOB is generally around 8.2 bits achieving a scaled figure-of-merit (SFoM) better than 3.0 Ç/c-s.

In multi-electrode arrays (MEAs), for electrical recording and electrical stimulation, high voltage (HV) switches are employed to build an analog multiplexer to conduct either a HV stimulation signal from the pulse generator circuit to an electrode or a low-voltage noise-sensitive signal from the electrode to a recording stage. In this brief, a new circuit structure is proposed for HV switches that significantly improves their switching speed, reduces their power dissipation, and also employs a minimum number of bulky HV devices. In order to reduce the transition time of the proposed switch without consuming a large amount of power, during the transition time that the switch is turning on/off, a large current flows through the driver circuit of the switch to turn the switch on/off rapidly; however, after the transition times, this current is significantly reduced to save power. Based on the proposed HV switch, a multiplexer structure has been implemented in 25-V, 0.18- μm CMOS IC technology and the measurement results prove its efficacy. Supplied with 25 V and operating with 300 nA current consumption, this switch swings over 20 V with a relatively constant on-resistance of 100Ω and features a 80 ns transition time.

This letter proposes a new level-shifting structure that can convert extremely low levels of input voltages to high output voltages while maintaining excellent delay and power dissipation. In order to reduce contention and voltage swing in the internal nodes, the proposed circuit uses a diode-connected level shifter between gate terminals of the output inverter. Using a control circuit, only during the high-To-low transitions of the output, a current is forced into the diode-connected device. Measurement results demonstrate that the proposed circuit can consume as small energy as 4.2 fJ/transition with VDDL and VDDH of 0.35 V and 1.1 V, respectively, when implemented in a 40-nm CMOS technology. Furthermore, when fabricated in a 180-nm technology, the level-shifting circuit can convert VDDL as small as 80 mV to 1.8 V without using low-Threshold devices.

A novel signal-specific power-efficient analog-to-digital converter (ADC) is proposed for sensorinterface applications. Instead of digitizing each analog sample independently, the proposed ADC determines the digital code corresponding to each new input sample by digitizing the difference of two consecutive samples. Therefore, for the applications with low-varying input signals, such as image sensors and ECG readouts, the difference of two consecutive samples is much smaller than the ADC full-scale range for the majority of the input samples, the power consumption of the capacitive digital-to-analog converter, the comparator, and the digital circuits of the proposed ADC is saved due to reducing the ADC activity. The prototype was fabricated using a 0.18-μm CMOS technology. Measurement results of 1 V, 8 bit, 20 kS/sADC confirm that for a 10-kHz input sine wave, the effectivenumber of bits is 7 while the power consumption of the entireADC is 1.12 μW. However, for the same sampling rate, the power consumption is only 106 nW for a low-varying 100-Hzinput sine wave.