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Y. Liu

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5 records found

Journal article (2020) - Alessandro Urso, Yue Chen, Robert Bogdan Staszewski, Johan F. Dijkhuis, Stefano Stanzione, Yao-Hong Liu, Wouter A. Serdijn, Masoud Babaie
In this paper, we propose a new scheme to directly power a 4.9-5.6GHz LC oscillator from a recursive switched-capacitor DC-DC converter. A finite-state machine is integrated to automatically adjust the conversion ratio and switching frequency of the converter such that its DC output voltage is within ±5% of the desired 1V across input voltage range 1.3-2.2V and < 2mA load current conditions. A gate-driver circuit is embedded in each switch of the converter to guarantee constant on-resistance across PVT variations without sacrificing device reliability. Furthermore, a spur reduction block (SRB) is embedded in the oscillator to suppress the ripple induced spurs by stabilizing its tail current. Both the converter and the oscillator are implemented in 40-nm CMOS technology. The measured peak power efficiency of the converter is 87%, while its spot noise is < 1.5nV/Hz which does not degrade the phase noise of the oscillator. The SRB suppresses the spur to <-65dBc under the 30mVpp ripple of the converter. ...
Journal article (2018) - Yao Liu, Wouter A. Serdijn
This paper presents the analysis and design of a passive front-end (PFE) for low-power receivers. The freedom of the antenna impedance is observed and exploited to propose an inductive-antenna-based PFE. Analytical methods for the desired signal transfer and noise behavior of the proposed PFE are presented to offer insight into the proposed technique and facilitate the design. The analysis suggests that the inductive-antenna-based PFE offers higher voltage gain and lower noise figure than a standard 50 &#x03A9;-based PFE does, which is confirmed by simulations. The proposed PFE and a baseband bandpass amplifier are designed in 0.18-&#x03BC;m CMOS technology for the 402-405 MHz band of the IEEE 802.15.6 WBAN standard. Their combination exhibits a passive voltage gain of 11.6 dB, a NF of 14.7 dB, and an in-band IIP3 of 3.6 dBm, while dissipating 1.1 mW from a 1.2 V supply. ...
Conference paper (2018) - Jiawei Xu, Qiuyang Lin, Ming DIng, Yao Li, Chris Van Hoof, Wouter Serdijn, Nick Van Helleputte
Simultaneous measurement of Electrocardiogram (ECG) and bio-impedance (BioZ) via disposable health patches is desired for patients suffering from chronic cardiovascular and respiratory diseases. However, a sensing IC must consume ultra-low power under a sub-volt supply to comply with miniaturized and disposable batteries. This work presents a 0.6 V analog frontend (AFE) IC consisting of an instrumentation amplifier (IA), a current source (CS) and a SAR ADC. The AFE can measure ECG and BioZ simultaneously with a single IA by employing an orthogonal chopping scheme. To ensure the IA can tolerate up to 300mVpp DC electrode offset and 400mV pp common-mode (CM) interference, a DC-servo loop (DSL) combined with a common-mode feedforward (CMFF) loop is employed. A buffer-assisted scheme boosts the IA's input impedance by 7x to 140MΩ at 10Hz. To improve the BioZ sensitivity, the CG utilizes dynamic element matching to reduce the 1/f noise of the output current, leading to 35mΩ/√Hz BioZ sensitivity down to 1Hz. The ADC shows a 9.7b ENOB when sampled at 20ksps. The total power consumption of the AFE is 3.8μW. ...
Journal article (2017) - Leila Rajabi, Mehdi Saberi, Yao Liu, Reza Lotfi, Wouter A. Serdijn
Phase-domain Analog-to-Digital Converters (Ph-ADCs) have been considered for power-efficient implementation of body-area network transceivers employing phase demodulation. Conventional implementations of the Ph-ADCs, which work based on a full-flash zero-crossing algorithm, use linear resistive/current combiners to determine the thermometer digital code of the signal phase. These architectures suffer from high-accuracy requirements, high-circuit complexity, and high-power consumption. Therefore, in this paper, a new IQ-assisted binary-search algorithm is proposed for implementing the Ph-ADC. The proposed Ph-ADC architecture avoids employing the power-hungry linear combiner. Moreover, for an N-bit Ph-ADC, the proposed algorithm requires only N +1 comparisons, whereas the conventional full-flash counterpart demands 2N-1 comparisons. Based on the proposed architecture, two different 5-bit charge-redistribution Ph-ADC s are designed and one of them is fabricated in a standard 0.18-μm CMOS technology. The prototype achieves an ENOB of 4.85 bits at 1 MS/s, while dissipating 12.9 μW from a 1.2-V supply. ...

Exploiting Non-50 Ω Antenna Impedance and Phase-Only Quantization

Doctoral thesis (2017) - Yao Liu
Reducing the power consumption of low-power short-range receivers is of critical importance for biomedical and Internet-of-Things applications. Two interesting degrees of freedom (or properties) that have not been fully exploited in the pursuit of low power consumption are the antenna impedance and the phase-only modulation property of FSK/PSK signals. This dissertation explores the possibility of reducing the power consumption of the receiver by utilizing these two degrees of freedom. ...