A Capacitively Degenerated 100-dB Linear 20-150 MS/s Dynamic Amplifier

Journal article (2018)

Authors

S. Akter Broadcom Netherlands B.V.
K.A.A. Makinwa Microelectronics
K. Bult Electronic Instrumentation - EEMCS
Department
Microelectronics
Copyright: © 2018 S. Akter, K.A.A. Makinwa, K. Bult
DOI: https://doi.org/10.1109/JSSC.2017.2778277
Amplifier Analog linearization technique Analog-to-digital converter (ADC) Capacitive degeneration Cross-coupled capacitors Digital nonlinearity calibration Dynamic residue amplifier Integrator Split-capacitor technique
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Published Date

2018

Language

English

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Department

Microelectronics

Abstract

This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to the state of the art, it exhibits 25 dB better linearity with twice the output swing and similar noise performance. The key to this performance is a new linearization technique based on capacitive degeneration, which exploits the exponential voltage-to-current relationship of MOSFET in weak inversion. The prototype amplifier is fabricated in a 28-nm CMOS process and dissipates only 87 μW at a clock speed of 43 MS/s, thereby improving the energy per cycle by 26 × compared with that of state-of-the-art high-linearity amplifiers.