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This thesis describes the design and implementation of power-efficient discrete-time amplifiers for data converter systems.@en
This brief presents a linearization technique for open-loop amplifiers. It utilizes the exponential {V}{-}{I} transfer of MOS transistors in weak-inversion together with a weak form of resistive degeneration. By using a specific relationship between the input transconductance ...
This paper presents a new dynamic residue amplifier topology for pipelined analog-to-digital converters. With an input signal of 100 mVpp,diff and 4 × gain, it achieves-100-dB total harmonic distortion, the lowest ever reported for a dynamic amplifier. Compared to t ...
This paper presents a closed-loop class-AB residue amplifier for pipelined analog-to-digital converters (ADCs). It consists of a push-pull structure with a ``split-capacitor'' biasing circuit that enhances its power efficiency. The amplifier is inherently quite linear, and so inc
...
This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp,diff and 4x gain, it achieves -100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB
better linearity with >2x larger output s
...
This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp,diff and 4x gain, it achieves -100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB
better linearity with >2x larger output s
...