A Capacitively-Degenerated 100dB Linear 20-150MS/s Dynamic Amplifier

Conference paper (2017)

Authors

S. Akter Broadcam Netherlands

K.A.A. Makinwa Microelectronics

Klaas Bult External organisation

Department

Microelectronics

Calibration Current measurement Linearity Clocks Capacitors Harmonic analysis Gain

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Published Date

2017

Language

English

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Department

Microelectronics

Abstract

This paper presents a new dynamic residue amplifier for pipelined ADCs. With an input of 100mVpp,diff and 4x gain, it achieves -100dB THD, the lowest ever reported in dynamic amplifiers. Compared to the state-of-the-art, it exhibits >25dB
better linearity with >2x larger output swing and similar noise performance. The key to this is a new linearization technique based on capacitive-degeneration. Fabricated in a 28nm CMOS, the prototype amplifier dissipates 87μW at a clock
speed of 43MS/s and maintains -100dB THD up to 150MS/s.

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