Quality and Cost Modeling Of 3D Stacked ICs

Abstract

Since the 1960s, the semiconductor industry’s rate of progress has followed by what is commonly known as Moore’s law. In recent years, the traditional approach of downscaling the feature size and increasing the operating frequency of the devices to improve the performance is slowing down due to the reaching of physical limits. Different solutions have been proposed to increase the performance such as using multi-core platforms, able to work in parallel. However, this introduced other issues such as a high latency and power dissipation due to the long communication distances. To overcome this, 3D Stacked ICs have been proposed, allowing for shorter vertical interconnects and higher transistor density. With the introduction of 3D stacked ICs (3D-SIC), the manufacturing processes and its test flow become more complex. As each chip requires to be tested prior to deployment, its crucial to find optimal test flows.
Developing an effective test strategy for 3D SICs is a complex task. During a 2D process, there are typically two test moments (i.e., wafer test and packaging test). However, for a 3D process, the number of possible moments grows based on the number of dies in the stack as many partial stacks test can be performed. In addition, also the interconnects between the stacked dies can be tested, as they play a crucial role in determining the correct functioning of the device. Testing such a partial stack may reduce the cost as it prevents good dies being stacked on them, but on the other hand may increase the total cost due to extra test costs. To help making such decisions, appropriate cost models are required. They are tools used to estimate the cost of a test flow typically applied at an early design stage. The information obtained from them can then be used to optimize the process in question and reduce the cost.
In this thesis, the functionality of 3D COSTAR is extended. 3D COSTAR is a tool developed with the goal of modeling the complete 3D SIC supply chain, including design, manufacturing, test, packaging and logistics. This thesis first presents a test flow optimization algorithm. It is used to evaluate and find the best test strategy, i.e., the highest fault coverage at the lowest cost. Second, a stacking order analysis is performed in which the impact of different stacking orders is evaluated. The goal is to evaluate whether a different stacking order reduces the overall cost. We evaluated both extensions using three case studies. Overall, lower cost solutions were found across all three cases. With respect to test flow optimization, cost reductions of 4%, 6% and 27% were obtained for the three case studies. With respect to stacking order analysis, a cost improvement up to 16% was realized.