A Multi-Path Sigma Delta ADC

Abstract

This thesis presents the design and testing of a multi-path analog-to-digital converter for current sensing in battery management systems. The specifications of this converter are (1) continuously integrate and convert a signal at 125 Hz with a resolution of 20 bit and (2) perform on demand fast conversions of 20 μs at a resolution of 14 bit. Both conversions should be done with a maximum 1 LSB offset and 0.1 % gain error. The realized system consists of a discrete time 1st order sigma delta converter, followed by a 10 bit charge redistribution extended counting ADC. This design uses the same analog front end for both conversions, thereby saving both power and chip area. To achieve the lowest offset possible, a system level chopping scheme is implemented. A working prototype has been made in TSMC 0.18 BCD technology, using an area of 570 μm × 150 μm with a 5 V supply voltage. The realized chip proves that the concept of combining the analog front end works and achieves a 15 bit linearity. At the 20 bit level, there are still significant issues and despite serious efforts the root cause of those issues has not yet been isolated. Next design and testing steps have however been identified.