A Continuous-Time Zoom ADC for Audio Applications based on a High-Linearity OTA and a 4-bit SAR ADC

A Continuous-Time Zoom ADC for Audio Applications based on a High-Linearity OTA and a 4-bit SAR ADC

Mehrotra, Shubham (TU Delft Electrical Engineering, Mathematics and Computer Science)

Makinwa, K.A.A. (mentor)
Eland, E.N. (graduation committee)

Delft University of Technology

Electrical Engineering

2021-11-25

Analog-to-Digital Converters (ADCs) used in high fidelity audio applications require high linearity and a wide dynamic range (>100 dB). Moreover, for use in portable electronic devices such as smartphones, tablets, and hearing aids, these ADCs must also achieve high energy efficiency. This requirement of high linearity and high energy efficiency can be fulfilled by zoom ADCs, which combine a successive approximation register (SAR) ADC and a delta-sigma modulator (∆ΣM) in a single architecture. Previous discrete-time zoom ADCs achieved these specifications with state-of-the-art energy efficiency, but their switched-capacitor front-ends necessitated power-hungry off-chip input drivers. A continuous-time (CT) zoom ADC solved this problem and achieved high energy efficiency, but its first integrator dominated the power consumption to meet the linearity requirements. Moreover, quantization noise leakage from the coarse SAR ADC (also referred to as “fuzz”) and distortion caused by parasitic resistance in the reference path limited its linearity. This work addresses these limitations of the CT zoom ADC and attempts to improve its energy efficiency and SNDR performance.

Combining the merits of previous state-of-the-art zoom ADC designs, this work features an energy-efficient CT zoom ADC with a 24 kHz bandwidth. Compared to the prior art, this work uses a highly linear OTA in the first integrator to meet the linearity requirements with lower power consumption. A 4-bit SAR ADC is used as a coarse quantizer, which reduces the digital power consumption and improves ADC’s robustness to the out-of-band interferers.

A prototype chip has been fabricated in standard 160nm CMOS technology. It achieves 107.2 dB peak SNR, 106.3 dB peak SNDR, and 107.3 dB DR in a 24 kHz bandwidth while consuming 590 µW. This translates to a Schreier figure-of-merit (FOMS) of 183.4 dB and FOMSNDR of 182.4 dB.

Hybrid ADC
Zoom ADC
OTA
High Resolution ADC
SAR ADC

http://resolver.tudelft.nl/uuid:88cc07fc-5938-457d-8db5-aafe50e359b6

2026-11-25

Student theses

master thesis

© 2021 Shubham Mehrotra