Designing Asynchronous Gate Library with new System Level Trade-offs

Abstract

This dissertation describes an approach to building a self-timed asynchronous pulse-mode serial link circuit. Unlike asynchronous handshake circuits or synchronous circuits, this design style does not require any feedback control blocks, which can increase latency, or any clock recovery circuits, which can increase energy consumption and overhead. In addition, the serial link design strategy can reduce resource consumption and the complexity of wire and pins to facilitate placement and routing. In this dissertation, a self-timed asynchronous circuit is used, which necessitates the usage of the pulse logic family. The link also includes the two-wire burst mode protocol. The time notion is included in the zero-line and one-line of the link, and the timing information is included in the transmitted pulse signal without the use of a clock.

The overall design process follows a hierarchical structure. Firstly, to achieve the logic function, the link is designed at the behavior level with VHDL code. The serializer and deserializer functions should therefore be performed at the transistor level. They are based on the pulse-logic library, which should be built initially. The transistors utilized in the design are all HVT transistors, which reduce current leakage and power consumption. The final step is to do timing characterization and optimization to ensure that the design works properly under various conditions. The entire point-to-point link can be built by using 28nm technology and can function at 5Gb/s with a power consumption of 0.5mW.