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Balanced Dual-Mask Protection Scheme for GIFT Cipher Against Power Attacks
Smart Redundancy Schemes for ANNs against Fault Attacks
Referencing-in-Array Scheme for RRAM-based CIM Architecture
RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs)
Advances in Magnetics Roadmap on Spin-Wave Computing
Would Magnonic Circuits Outperform CMOS Counterparts?
Rapid Design-Space Exploration for Low-Power Manycores under Process Variation utilizing Machine Learning
Recent Trends and Perspectives on Defect-Oriented Testing
Special Session: STT-MRAMs: Technology, Design and Test
Multi-frequency Data Parallel Spin Wave Logic Gates
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM
Protecting IoT Devices through a Hardware-driven Memory Verification
Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron
Improving the Detection of Undefined State Faults in FinFET SRAMs
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs
Spin Wave Normalization Toward All Magnonic Circuits
Review of Manufacturing Process Defects and Their Effects on Memristive Devices
Multi-level control of resistive ram (Rram) using a write termination to achieve 4 bits/cell in high resistance state
LightRoAD: Lightweight Rowhammer Attack Detector
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography
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