Meta-learning for few-shot on-chip sequence classification

The growing interest in edge computing is driving the demand for more efficient deep learning models that fit into resource-constrained edge devices like Internet-of-Things (IoT) sensors. The challenging limitations of these devices in terms of size and power has given rise to the field of tinyML, focusing on enabling low-cost machine learning...

Real-Time Detection and Classification of Purkinje-Cell Neural Activity

Purkinje cell is a type of neuron that can be found in the cerebellum. What characterises Purkinje cell neural activity is the fact that it exhibits two types of spiking behaviour; the so-called simple and complex spikes. These two types of spikes are thought to play a role in motor functionality. In order to better understand the relationship...

Design of an FMCW-LiDAR receiver front-end

This work presents an analog front-end (AFE) signal processing chain for automotive FMCW LiDAR. The AFE consists of a high-gain transimpedance amplifier (TIA) followed by a gain-stage. The gain of the AFE is 103.2dBΩ at a bandwidth of 505MHz. Since the noise of FMCW-LiDAR systems is dominated by the shot noise of the local oscillator (LO), the...

Exploring Feasibility of FPGAs in Implantable Medical Devices

Implantable Medical Devices (IMDs) are deployed in patients to treat a range of medical conditions. Technological advancements have enabled manufacturers to fit IMDs with specialized hardware that accelerates compute-intensive medical therapies next to a software-run host processor. However, mostly hardware acceleration is found in the form of...

ρ-VEX ASIC: The Design of an ASIC for a Dynamically Reconfigurable VLIW Processor with 24-port Register File

The ρ-VEX is a runtime reconfigurable VLIW processor. It is able to exploit both ILP as well as TLP by running one program in multiple lanes, or several programs concurrently. To accurately quantify its performance compared to other processors, it is implemented as an IC.<br/>A fully automatic scripted flow is described, constructing an...

Exploring suitable Adder Designs for Biomedical Implants: A gracefully-degradable, fault-tolerant, and highly resource-constrained adder for SiMS

Modern applications demand extremely low power budgets in computer architectures for battery-operated devices. In the particular case of implantable devices —the main focus of this thesis— the system must have a long life span and batteries may not be possible or easy to recharge. In addition to power, chip area is also of major concern in this...