Cryogenic-Aware Forward Body Biasing in Bulk CMOS

Cryogenic CMOS (cryo-CMOS) circuits are often hindered by the cryogenic threshold-voltage increase. To mitigate such an increase, a forward body biasing (FBB) technique in bulk CMOS is proposed, which can operate up to the nominal supply without problematic leakage currents, thanks to the larger diode turn-on voltage at cryogenic temperatures...

A Cryo-CMOS SAR ADC With FIA Sampling Driver Enabled by Cryogenic-Aware Back-Biasing

This paper presents a floating inverter amplifier (FIA) that performs high-linearity amplification and sampling while driving a 2<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> time-interleaved (TI) SAR ADC, operating from room temperature (RT) down to 4.2 K. The power-efficient FIA...

A Cryo-CMOS Oscillator With an Automatic Common-Mode Resonance Calibration for Quantum Computing Applications

This article presents a 4-to-5GHz LC oscillator operating at 4.2K for quantum computing applications. The phase noise (PN) specification of the oscillator is derived based on the control fidelity for a single-qubit operation. To reveal the substantial gap between the theoretical predictions and measurement results at cryogenic temperatures, a...

Characterization and modeling of mismatch in Cryo-CMOS

This paper presents a device matching study of a commercial 40-nm bulk CMOS technology operated at cryogenic temperatures. Transistor pairs and linear arrays, optimized for device matching, were characterized over the temperature range from 300 K down to 4.2 K. The device parameters relevant for mismatch, i.e., the threshold voltage and the...

The electronic interface for quantum processors

Quantum computers can potentially provide an unprecedented speed-up with respect to traditional computers. However, a significant increase in the number of quantum bits (qubits) and their performance is required to demonstrate such quantum supremacy. While scaling up the underlying quantum processor is extremely challenging, building the...

Characterization and Compact Modeling of Nanometer CMOS Transistors at Deep-Cryogenic Temperatures

Cryogenic characterization and modeling of two nanometer bulk CMOS technologies (0.16-μm and 40-nm) are presented in this paper. Several devices from both technologies were extensively characterized at temperatures of 4 K and below. Based on a detailed understanding of the device physics at deep-cryogenic temperatures, a compact...