A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The...

A Ring-Oscillator Sub-Sampling PLL With Hybrid Loop Using Generator-Based Design Flow

We present a ring-oscillator-based sub-sampling phase-locked loop (PLL) using a generator-based design flow. A hybrid loop with a delta-sigma ($\Delta \Sigma$) modulator is applied to reduce the loop filter (LF) area and the control ripple. The generator automatically produces the ring oscillator and PLL to meet the provided specifications. The...

Generating sparse self-supporting wireframe models for 3D printing using mesh simplification

Wireframe models are becoming a popular option in 3D printing. Generating sparse wireframe models using classic mesh simplification methods leads to models that require a lot of support structures in the layer-upon-layer additive process. In this paper we present a mesh simplification method that takes into account the overhang angle....

Cross section-based hollowing and structural enhancement

Recently, 3D printing has become a powerful tool for personal fabrication. However, the price of some materials is still high which limits its applications in home users. To optimize the volume of the model, while not largely affecting the strength of the objects, researchers propose algorithms to divide the model with different kinds of...