Implementation and Evaluation of Packed-SIMD Instructions for a RISC-V Processor

With the increase in the amount of data being gathered, the need for data processing is also rising. Furthermore, in addition to the proprietary ISAs that have been prevalent, the free and open RISC-V ISA has seen major interest. The modularity of the RISC-V ISA allows it to be extended with many instruction set extensions. One such extension...

Accelerating Software Pipelines Using Streaming Caches

The trend of increasing performance by parallelism is followed by the adoption of heterogeneous systems. In order to allow more fine-tuned balancing between used thread- and instruction level parallelism, the heterogeneous ρ-VEX platform was developed. Pipelining has been a part of microprocessor development for decades to increase throughput of...

Streaming FPGA Based Multiprocessor Architecture for Low latency Medical Image Processing

In this work a fast and efficient implementation of a Field Programmable Gate Array (FPGA) based, fixed hardware, streaming multiprocessor architecture for low latency medical image processing is introduced. The design of this computation fabric is based on the ρ-VEX Very Long Instruction Word (VLIW) softcore processor and is in influenced by...